06.4 Memory

General Properties

In RISC-V, we need 32 bits to represent the address of memory.

The data width within the memory is of 1 Byte

The total memory is the number of addresses x the width of the data:

$$2^{32}\times \text{Byte}$$

Definition

We say that memory is byte-addressable ⇒ one address = one byte

Name	Size	Bytes
Byte	$8$ bits	$1$
Halfword	$16$ bits	$2$
Word	$32$ bits	$4$
Quadword	$128$ bits	$16$
We can represent memory visually by either drawing the higher indexes at the top, or the higher index at the bottom. Both ways are interchangeable without consequences.

One instruction occupies one word

This means that the program counter will increase by $4$ after each step

Byte Ordering

How do we represent words in memory? Should the first byte be represented as the lowest part in memory (little endian), or the highest part (big endian)?

Little Endian

The least significant bit is stored at index $0$

Big Endian

The most significant bits of the word are stored at the lower memory address

Instruction Encoding

Example

Encoding the instruction 00 73 52 B3

• Little Endian:

We get the lowest byte (B3) and put it at the lowest index of memory, and go up with each word:

Addr: 0x00 | 0x01 | 0x02 | 0x03 | ...
Mem : 0xB3 | 0x52 | 0x73 | 0x00 | ...

• Big Endian:

We get the biggest byte (00) and put it at the lowest index of memory, and go up with each word:

Addr: 0x00 | 0x01 | 0x02 | 0x03 | ...
Mem : 0x00 | 0x73 | 0x52 | 0xB3 | ...

Load and Store

Memory read/write operations are called load/store

We have — in RISC-V — the instructions for loading signed and unsigned

• bytes: lb, lbu
• words: lw

imm	rs1	funct3	rd	opcode
12	5	3	5	7
offset	base register index	3 bit function code	destination index	7bit operation code OP

Similarly, we can store:

• bytes: sb
• words: sw

imm	rs2	rs1	funct3	rd	opcode
7	5	5	3	5	7
offset	base register index	register recieving value	3 bit function code	destination index	7bit operation code OP

06.5 Branches