Modeling of Digital Circuits in Verilog
A logic circuit is specified in the form of a module We have two options :
- Structural modeling :
- We use verilog to describe the structure of the circuit
- A larger circuit can be defined by writing code that instantiates and connects circuit elements
- Behavioral modeling :
- Describe a circuit more abstractly, using logic expressions to describe the desired behavior
Structural Modeling
Predefined modules that implement basic gates are used We instantiate it as such:
gate_name [instance_name] (out, in_port{..., in_port});Square brackets indicate optional field, squigly indicate that additional entries are allowed
Syntax
Names
- Must start with a letter
- Can contain any letter, number, underscore or ’$’ Verilog is case sensitive Syntax does not enforce a style
- whitespace is ignored
- indentation does not matter
- // starts a comment
Modules
A circuit or subcircuit is a module A module has a name, ports(inputs and outputs)
- We declare which ports are input or outputs :
input a;
output f;- We can declare wires
- We can instantiate gates
- Modules
- Etc..
We declare the direction of ports:
- input
- output
- inout (both input and output)
We can declare the size of the inputs
input a; //1-bit wire
inout [15;0] data; // 16-bit vector wire