05.2 Finite State Machines

Circuits that contain both combinational and sequential logic have a state => we call them state machines

The amount of states is finite => we call them finite state machines — FSM for short

Mealy FSMs

A Mealy state machine (named after George H. Mealy), has

• A next state logic $f(\dots )$
  • A function of inputs and current state -> for the next state
• State memory
  • A set of $n$ flip-flops that store the current state
• Output logic $g(\dots )$
  • A function of inputs and current state -> to output as a result

In verilog, we have an always block for each part :

• Next state => always @(*)
• State memory => always @(posedge CLK)
• Output logic => always @(*)

Moore FSM

A Moore state machine (named after Edward F. Moore), has

• A next state logic $f(\dots )$
  • A function of the current state and inputs
• State memory
  • A set of $n$ flip-flops that store the current state
• Output logic $g(\dots )$
  • A function of the current state does not depend on inputs

In verilog, we model it in the same way — but make sure inputs don’t influence directly the outputs

State Machine Analysis

We often use diagrams to analyse state machines => state diagram

• A graph that shows states and transitions between states

On a node we have edges (arrows), as well as the output variables