In a single-cycle CPU, operations take only one clock cycle.

Implementation of a Single-Cycle CPU

Let’s only try to implement a small subset of the operations.

Instruction memory

An external memory that stores the instructions

  • Higher capacity than the register file
  • Byte addressable

Program counter accesses an address of an instruction

We also need an adder to go to the next instruction

General purpose registers

We have general purpose registers of bits in a register file

Register are read from/written to by specifying the index of the register

  • We need to be able to read 2 registers and write to 1 other at the same time (R-format instructions)

We also need a signal if we want to write to a register

ALU

The unit that does the arithmetic operations

It takes two -bit inputs, and produces a result of -bits, as well as some flags

  • A flag could per example be whether the output is

The ALU operation signal determines which operation to do, and is over bits.

Data memory load/store

We need to be able to write to larger memory than the register file

We have:

  • A -bit address input
  • A -bit write data input
  • A -bit read data output
  • -bit signal to say that we want to read
  • -bit signal to say that we want to write

We need to be able to generate immediate for load and store offsets, as operations only have -bits for the immediates

Branch support

We have instructions that allow to branch/jump to other sections of the instructions

We can use the previously introduced zero flag to check for equality, and branch accordingly.

Control signals

The missing signals (in blue in the previous schematics) are defined by a control unit: It determines what instruction to use.

The missing signals are:

RegwriteALUSrcPCSrcMemReadMemWriteMemtoReg
The register assigns a value to a registerDetermines whether the ALU takes a register or an immediateDetermines how to increment the program counterWhether to read a value from memoryWhether to write a value to memoryWhether to load a value from memory

Per example, to define what value the program counter increases by, we have an AND gate between the mux of the operation (to determine if the instruction is branch) and the ALU’s zero flag

TLDR

07.2 Multi-cycle CPU