05.3 Memory

Decoder

A decoder is a logic circuit that receives $n$ bits and produces $2^n$ bits, where only one bit is set to one

That bit is “hot”

We have the truth table given by

$$\begin{array}{cccccc}{w}_1& w_0& y_0& y_1& y_2& y_3\\ 0& 0& 1& 0& 0& 0\\ 0& 1& 0& 1& 0& 0\\ 1& 0& 0& 0& 1& 0\\ 1& 1& 0& 0& 0& 1\end{array}$$

We can also have an enable signal (which means that the vector $y=0$ when enable is $0$)

Larger decoder can be constructed from smaller decoders

Memory

Memory allows to store bits. There are a lot of different implementations of memory.

We can represent memory as a two dimensional array. Where

• One memory element is at a row $i$, and is called a data word (vector of bits)7

We call that index the address.

We typically store data in bytes ($B$) (8-bit vectors) ⇒ Capacity is the amount of bytes it can store

We have units:

Unit	Bytes
Kilobyte	$2^{10}$
Megabyte	$2^{20}$
Gigabyte	$2^{30}$
Terabyte	$2^{40}$

Access protocols

We have multiple protocols for accessing memory.

We will consider a simple protocol:

• Synchronous write (on clock posedge)
• Asynchronous read

Array of 4x4 DFFs

In Verilog

⇒ 1D Array of Registers;

We can declare an array of $w$ words of $b$ bits as:

reg [b-1:0] memory [w-1:0];

To allow for modules where we can modify the width of vectors dynamically, we can use the parameter keyword:

// Set the default parameter of WIDTH to 1
parameter WIDTH = 1;
 
// Which allows use to instantiate the module with different widths
modulename #(.WIDTH(8)) instancename (/* ... */);