05.1 Synchronous Systems Timing Constraints

In practice, the outputs of sequential logic elements connects to the inputs of other sequential elements.

For correct operations, timing constraints must be met.

A signal on input $D$ of a DFF must be stable during (before and after) the rising edge of the clock (so that the correct data gets read)

Metastability

If a signal is not stable around the rising clock edge, then a DFF will oscillate at a value between $0$ and $1$, before settling on a random value.

For a circuit to meet those timing constraints, then all FF outputs to FF inputs must meet timing constraints. In order to do so, we:

• Must have a stable signal for $t_{\text{setup}}$ before and $t_{\text{hold}}$ after the rising clock edge

A signal goes through a few steps:

Born as $Q$ of the source FF

There can be a delay $t_{cQ}$ between $t_{cQ,\min }$ and $t_{cQ,\max }$

Updating the output takes some clock-to-$Q$ delay

Journey through combinational logic

It takes time of $t_{\text{comb}}$ for the signal to be processed during the combinational logic.

During this time the signal outputted can be unstable

Arrives at the Destination FF

After a total time of $t_{cQ}+t_{\text{comb}}$, the signal arrives at the destination where it will be captured

Waits to be captured

It waits — in a stable manner — at the input of the next flip flop. This wait must at least be as long as the setup time $t_{\text{setup}}$

Gets captured on the clock edge

The destination takes the value on its input, and works through memorizing it. (Which can take some time)

Waits to be replaced

The clock edge that captured is passed. The wait must be at least as long as the hold time $t_{\text{hold}}$ (And it must be stable!!).

Meeting time constraints

To setup the signal, we have the following:

For $t_{cQ}$ and $t_{\text{comb}}$, we must have the inequality given by

$$T_{\text{CLK}}-(t_{cQ}+t_{\text{comb}})\ge t_{\text{setup}}$$

The worst case time constraint can be rewritten as

$$\boxed{t_{cQ,\max }+t_{\text{comb},\max }+t_{\text{setup}}\le T_{\text{CLK}}=1/f_{\text{CLK}}}$$

We have an algorithm to find this maximum frequency $f_{\max }$

Algorithm

1. Identify all $Q$-to-$D$ paths
2. For every path a. Compute its longest combinational delay b. Find the shortest clock period that satisfies this path’s setup-time constraint
3. Find the shortest clock period $T_{\text{CLK}}$ that satisfies the setup-time constraints of all those paths
4. Compute $f_{\max }=1/T_{\text{CLK}}$

To hold the signal, we have the following:

For $t_{cQ}$ and $t_{\text{comb}}$, we have:

$$t_{cQ}+t_{\text{comb}}\ge t_{\text{hold}}$$

The worst-case constraint is written as

$$\boxed{t_{cQ,\min }+t_{\text{comb},\min }\ge t_{\text{hold}}}$$

To find hold-time violations, we have

Algorithm

1. Identify all $Q$-to-$D$ paths
2. For every such path a. Compute its shortest combinational delay b. Verify if the hold-time constraint is satisfied

Clock Skew

In real circuits, the clock signal may not arrive at all FFs at the same time, due to the wires

We call this delay clock skew — which is given by

$$t_{\text{skew}}={\Delta }_D-{\Delta }_S$$

This should not be neglected!!

We have both a negative and a positive clock skew

• Negative: $t_{\text{skew}}<0$
• Positive: $t_{\text{skew}}>0$

With clock skew, we see life of the D signal change slightly, as we need to account for the possible delays in clocks for the hold and the setup time

The expression that must hold has the skew added in:

$$T_{\text{CLK}}+{\Delta }_D-({\Delta }_S+t_{cQ}+t_{\text{comb}})\ge t_{\text{setup}}$$

And we have the worst-case scenario as

$$t_{cQ,\max }+t_{\text{comb},\max }+t_{\text{setup}}-({\Delta }_D-{\Delta }_S)\le T_{\text{CLK}}=1/f_{\text{CLK}}$$

And to meet hold time constraints, we have

$$t_{cQ}+t_{\text{comb}}-({\Delta }_D-{\Delta }_S)\ge t_{\text{hold}}$$

And the worst-case scenario as

$$t_{cQ,\min }+t_{\text{comb},\min }-({\Delta }_D-{\Delta }_S)\ge t_{\text{hold}}$$

Positive time skew INCREASES max frequency

05.2 Finite State Machines