A bus is a shared wire / group of wires, which can only be used by one signal at a time.
They are typically bit wide,
In verilog we use vectors to represent buses
We use a tri-state driver to only enable the output of only one module at a time.
- Bidirectional buses
- Harder to verify and debug
- Slower on larger buses
- Timing control is tricky
- Off-chip communication
We can also use a MUX to choose which inputs are enabled
- Safe and clean
- Logic design tools understand muxes better
- Better for verification
- Unidirectional buses
- In-chip communication