03.5 Sequential Logic

A circuit that depends on its past values

→ Sequential circuits have memory

Latches

Basic memory element, we have $Q_{\text{next}}=\overline{\overline{S+Q}+R}$

A characteristic table describes the behavior of the sequential circuit, here :

$S$	$R$	$Q_{\text{next}}$
$0$	$0$	$f(S,R,Q)$
$0$	$1$	$f(S,R,Q)$
$1$	$0$	$f(S,R,Q)$
$1$	$1$	$f(S,R,Q)$

Depending on the value of the output, a latch can be in one of two states :

• $Q=0$
• $Q=1$

A state is a property of the memory element

The element described above is known as a set-reset latch

Let’s look into its states

$S$	$R$	$Q_{\text{next}}$	State
$0$	$0$	$Q$	Circuit state does not change (it is stable)
$0$	$1$	$0$	Output is reset to $0$
$1$	$0$	$1$	Output is set to $1$
$1$	$1$	$0$	Output is reset to $0$ ($R$ dominates)

We see that this circuit holds its state (memory !)

D Latch

A D latch is level-sensitive. While the signal $C$ is active, the output of $Q$ follows all changes taking place on $D$

Flip-Flops

We want tighter control of when the D latch activates.

A $D$ Flip-Flop is an edge sensitive memory elements → only activates when the clock signal has its rising edge

always @(posedge Clock) → used to describe sequential that trigger on a clock rising edge.

Only use non-blocking assignments <=

Clock

• A signal that determines when the state changes
• Typically defined by its frequency (or duty ratio)

Synchronous vs Asynchronous

A synchronous signal is one that is taken into account when the clock is switching states (rising or falling edge)

An asynchronous signal is one that immediately affects the output, regardless of the clock

Non-blocking assignments

Causes assignments within an always block to occur in parallel

Allows for modelling of sequential logic behavior ⇒ signals changing won’t affect each other.

Registers

A register is essentially a bunch of flip-flops, that store $n$ bits, one flip flop per bit.

Often we see a reset and a clock

A $n$-bit register has $2^n$ different values possible

Shift Registers

A shift register shifts the $n$-bit value one bit to the left or to the right

We chain $n$ registers, where the $i$-th register is bit of the number shifted $i$ times

We have a variant where we can choose (with a SEL into MUX) to set the data in parallel

Counters

A simple circuit that increments/decrements its value

(could be made using a add/sub by one, but it is too overkill)

• We have a single input choosing whether to turn on the counter
• We have an output vector $Q$ denoting the number
• We have a clock
• It resets back to 0 after $2^n$ clock cycles

It can again be desirable to start from another value than one, so we can once again use MUX and a LOAD signal to load a value into the registers in parallel

Loops

We can create for — while — repeat and forever loops in verilog

For loops are instantiated as in any other programming languages